This invention relates to fabrication of semiconductor integrated circuit (IC) devices, and more specifically to fabrication and testing of multi-chip modules.
Electrical testing of IC devices is a significant component of the cost of the final IC product. Considerable development and test tool investment is made in this aspect of IC manufacture. In Multi-Chip-Module (MCM) packaging, the test strategy is especially critical. Testing the final product, the conventional approach generally favored from the standpoint of both cost and reliability, is not optimum for MCM products since the final yield is a multiple of the yield for each individual die in the MCM package. For example, if each of the dies in the package has a yield of 95%, an MCM with 3 dies will have a yield of only 85.7%. Thus in some IC device packaging, notably MCM packaging, it is highly desirable to fully test the dies before assembly to identify the Known Good Dies (KGD). This typically involves both electrical functionality tests, and often aging or burn-in tests. Burn-in tests are especially important for memory dies, which typically exhibit a 1-5% burn-in failure rate over dies that have been only functionally tested. However, burn-in tests require robust and reliable electrical probe connections. Moreover, it is also useful to test these devices after the package interconnections are made. This provides not only the robust electrical contacts just mentioned but also allows the integrity of the package interconnections to be verified. This leaves a choice between providing only KGD prior to assembly, or assembling relatively untested devices and testing them after assembly. The first choice is costly since KGD are inherently expensive. The second choice involves the risks outlined earlier, i.e. the need to discard an MCM package with several good chips due to one defective chip.
Thus there exists in the technology a choice between assembling only known good die (KGD) or assembling largely untested chips and testing after assembly. Both choices have drawbacks.
We have developed an IC testing approach for MCM devices that marries the advantages of both of the choices just described. When, as usually the case, there are one or more IC chips of relatively low value but relatively high probability of failure that can easily be tested in packaged form, that selected device can be packaged first and tested. The IC chip or chips of relatively high value are fully tested prior to packaging and are then integrated into the partially packaged MCM. In the preferred embodiment, the relatively untested chips that are assembled first into the package are located on one side of an interconnect substrate and the later assembled chips are located on the other side of the interconnect substrate.